Design Verification Technical Lead

Design Verification Technical Lead

Efinix Technology (M) Sdn Bhd
5 - 15 Years
206133 - 274845 MYR

Job Description

As a Design verification technical lead, you will be responsible to define the comprehensive verification and validation plan covering block to fullchip and system level validation. You will also be responsible for carrying out design validation to ensure design full functionality from logic simulation, emulation prototyping to system level validation. In additional, you will be driving the verification methodology to improve the verification flow and reduce the verification time through automation.

• Create verification and validation plan based on IP/FPGA architecture specifications and carry out all the validation tasks. The plan should include functional, system level and fullchip verification and validation perspectives.
• Developing IP/subsystem/system level/fullchip testbench, create tests, and necessary coverage goals based on specification to verify the design.
• Lead the results review against the coverage goals. Track and improve the tests to ensure the desire coverage is met.
• Support cross-functional teams in IP functional validation tests for IP bring-up on actual FPGA.
• Standardizing verification and validation framework, drive system test design implementation and overall IP system validation on HW.
• Define and develop verification and validation tools and flows to reduce the verification time.
• Interfacing with 3rd party vendors for latest industry tool and methodology evaluation.
• Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time-to-market. 

• Bachelor's degree in Electrical, Electronics or equivalent.
• Experience in IC design verification.
• Experienced using advanced verification methodologies such as UVM, OVM, VMM, System Verilog, constrained-random verification, assertion-based verification, and functional coverage techniques is a strong plus.
• Experienced creating and executing validation plans.
• Experience of leading a verification or validation team.
• Familiar in RTL design with Verilog and/or VHDL is a strong plus.
• Knowledge of memory interface protocol (DDR, HBM, etc) or high speed interfaces (PCIe, Ethernet, etc) is a strong plus.
• Familiar with Perl, TCL and shell scripts is a plus.
• Exceptional analytical, problem solving and communication skills. Able to work independently.
• Demonstrates fundamental values such as accountability, integrity and a winning mindset.

Our mission is to drive the future of edge AI computing with our Trion® FPGA silicon platform. At the heart of Trion FPGAs is our disruptive Quantum™ technology, which delivers a 4X Power-Performance-Area advantage over traditional FPGA technologies. Trion FPGAs, offering 4K to 200K logic elements (LEs), have a small form factor, low power, and are priced for high-volume production. Our Efinity® Integrated Development Environment provides a complete FPGA design suite from RTL to bitstream generation.

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