Job Description :
Job Description /Other Requirements:
- Graduates from Electrical Engineering (EE) or Computer Science (CS).
- Strong background in ASIC design methodology and EDA tools for simulation and verification, synthesis, P&R, formal verification and static timing analysis.
- Strong coding skill in verilog/VHDL RTL and behavioral code, experience with SystemVerilog will be a plus.
- Experience with design through complete from RTL to GDS flow and familiar with ECO flow.
- Familiar with Linux Environment (including shell scripting and linux gnu tools).
- Scripting language experience a plus (perl, ruby, tcl, etc.).
- Have successfully defined, developed, and implemented digital logic.
- Ability to travel is a plus.
- Familiarity with Cadence/Mentor Graphics/Synopsys environment is a plus.
- Working experience in FPGA design and development software.
Highly self-motivated and excellent in problem solving and time management skills.
Able to work independently and in a team environment.
- Strong background in ASIC design flow [RTL to GDS].
- Strong coding skill in Verilog/VHDL for synthesisable RTL and behavioral modeling. SystemVerilog, Verilog-AMS is a plus.
- Strong verification skills using SVA, UVM, OVM, DFT.
- Scripting language experience a plus (perl, Makefile, bash, tcl, ... etc.).
- Familiar with C coding, MATLAB is a plus.
- Familiar with ECO flow, FMEA is a plus.
- Able to work independently and in a team environment.
Malaysians and Expants are welcome to apply.
Candidates must be willing to travel abroad
Candidates must be open for outsourcing to different locations apart from our primary locations ( Petaling Jaya and Penang)
Candidates must be willing to submit 3 recent paystubs while submitting resume.