Staff DFT Engineer

Staff DFT Engineer

Penang Malaysia
10-13 years
Not Specified

Job Description

Job Description :
Job Description
Custom Structured ASIC Engineering (CSAE) Design team develops next generation Intel structured ASIC products. In this position, the engineer will involve in verifying DFT feature, performing ATPG simulation and pattern generation, as well as fault coverage analysis. The engineer will also involve in architecture definition and influence the DFT implementation in the next generation eASIC structured ASIC products. The candidate will:
- Work with architecture team, IP team and Circuit team to understand design implementation and define DFT integration strategy for next generation silicon product, including high-speed I/O DFT, MBIST, LBIST and functional based DFT.
- Lead the definition and development of DFT flow to centralize the pattern generation methodology and verification for both DC & AC scans in bypass & edt mode, BIST and etc.
- Debug, analyze and provide innovative solutions to improve ATPG coverage in both Stuck-At and Transition Faults.
- Develop STA flow for shift & capture testmode and boundary scan mode.
- Involve in silicon bring-up testing and debug.
- Define DPPM calculation methodology and determine targeted ATPG coverage for each design
- Work with Test Engineering team to resolve ATPG pattern failures on ATE.
- Work with Test Engineering team to root-cause and provide ATPG patterns or advise targeted test to cover customer RMA.
- Work with worldwide design and research teams to influence the DFT/Test roadmap.
- Degree in Computer Science or Electrical/Electronic Engineering with minimum 10 years of working experience in VLSI DFT.
- Experience in Verilog/VHDL including behavior model construction and verification is essential
- Experience in Industrial ATPG tools, Logic simulation tools
- Experience in Perl, TCL, C/C++ and Linux/Unix software development will be added advantage
- Experience in static timing analysis tool such as PrimeTime will be added advantage.
- Strong knowledge of Computer Systems and Skills (a must).
- Industrial ATPG tools such as TestKompress, TetraMax, or Encounter Test
- Logic simulation tools such as VCS, Questa or NCVerilog
- JTAG and boundary-scan test methodology
- Experienced and good understanding of test compression.
- Memory BIST and Logic BIST
- High-speed I/O testing methodologyInside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

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